1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit used as a latch circuit or a shift register in the output stage of a memory.
2. Description of the Related Art
In recent years special-purpose memories have energetically been developed. In particular, large-capacity and low-cost DRAMs have the attention especially in the field of image processing in television or video.
Conventionally, where a DRAM is used for image storage, a parallel to serial conversion circuit adapted for reading and writing data had to be installed externally. Recently, however, a new type of DRAM has appeared which incorporates a shift register into a chip. With this type of DRAM data is read out of RAM in parallel to be transferred to the shift register, and data is then transferred from the shift register to the outside at high speed.
Since the operation speed of image memories is high (several tens of nanoseconds in cycle time), the high-speed operation capability and high reliability in operation are required of shift registers in the output stages of the memories.
FIG. 1 shows a prior art shift register.
This shift register combines a circuit 91 called a clocked inverter circuit and a flip-flop circuit 93 to form a latch circuit 90. The two latch circuits 90, 100 are connected in cascade. The preceding circuit 90 and succeeding circuit 100 are referred to as the master and slave, respectively. More specifically, clocked inverter circuit 91 comprises a CMOS inverter consisting of P-channel and N-channel MOS transistors P91 and N91 having their sources connected to a power supply voltage Vcc and a ground voltage Vss, respectively, and their gates connected together, and switching MOS transistors P92 and N92 connected between the gates of inverting transistors P91 and N91. Flip-flop circuit 93 consists of an inverter 95 and clocked inverter 94 as shown.
Further, switching transistors P92 and N92 of clocked inverter 91 in master section 90 have their gates connected to receive complementary clock pulses .phi. and .phi., respectively, and switching transistors P94 and N94 of clocked inverter 94 in flip-flop circuit 93 have their gates connected to receive complementary clock pulses .phi. and .phi., respectively.
On the other hand, the gates of switching transistors P102 and N102 of clocked inverter 101 in slave section 100 are connected to receive complementary clock pulses .phi. and .phi., respectively, and the gates of switching transistors P104 and N104 of clocked inverter 104 in flip-flop circuit 103 are connected to receive complementary clock pulses .phi. and .phi., respectively.
Hereinafter, the operation of the shift register configured by clocked inverters controlled by complementary clocks .phi. and .phi. will be described with reference to FIG. 2.
As shown in FIG. 2, at a time when clock .phi. is low (0V) and clock .phi. is high (5V), switching transistors P92 and N92 of clocked inverter 91 in master section 90 turn on together, so that the two CMOS inverters in the master section are operated to invert an input signal Vin, and a delayed output appears a node f. At this time switching transistors P94 and N94 in flip-flop circuit 93 turn off together. Switching transistors P102 and N102 in slave section 100 are off together so that the CMOS inverter therein is disabled. Switching transistors P104 and N104 in flip-flop circuit 103 are on together so that the previous state is held.
Next, at a time t2 when .phi. goes high, and .phi. goes low, switching transistors P92 and N92 in master section 90 turn off together. At the same time switching transistors P94 and N94 in flip-flop circuit 93 turn on to continue to hold data so far stored. Further, in slave section 100 switching transistors P102 and N102 turn on together to transfer data on node f to an output terminal OUT.
At a time t3, namely, when .phi. remains high and .phi. goes remains low, flip-flop circuit 93 in master section 90 keeps holding the stored data. Since switching transistors P92 and N92 in clocked inverter 91 are both off the output signal Vout will not change with a change in the input signal Vin.
Finally, at a time when .phi. goes low and .phi. goes high, switching transistors P102 and N102 in the slave section 100 turn off together, and switching transistors P104 and N104 in flip-flop circuit 103 turn on together. As a result flip-flop circuit 103 is activated to hold data. This data is data which was stored in master section 90 at time t3, and not new data. Thus, no change will occur in the output signal Vout. Moreover, in master section 90 switching transistors P92 and N92 turn on together, and in flip-flop circuit 93 switching transistors P94 and N94 both turn off. Thus, a new input signal Vin may be entered.
With the shift register as described above, the output signal Vout takes, under the second transient condition of clocks .phi. and .phi. as occurs at the time t2, a value of the input signal Vin and holds the value until the second condition occurs again.
To perform such an operation reliably, two clocks .phi. and .phi. are needed which are always to be completely opposite in polarity as shown in FIG. 2. It is difficult to generate such clocks. To generate such clocks will result in complexity in circuit arrangements, leading to an increase in chip area. Even if completely opposite polarity clock signals are externally applied, internal circuits cannot directly be driven by such externally applied clock signals. It is necessary to produce, within a chip, a signal synchronized with an externally applied signal, and a separate signal opposite in polarity to the produced signal through an inverter. Further, actual clocks have propagation delays in their rise and fall because of the gate capacitance, wiring capacitance or wiring resistance of circuits to be driven. The propagation delay times will vary drastically with the above capacitance and resistance, and the power supply voltage Vcc.
Accordingly, in case where the propagation delay times of the clock waveforms become long, and the two clock waveforms have a difference in their timing, a high-impedance state unique to the clocked inverters may occur in a transient state from the input-data-outputting state to the output-data-holding state. As the case may be, the output data might be inverted, causing a malfunction.
The high-impedance state will be specifically described hereinafter. Suppose now that an input signal Vin at input IN is low, clock .phi. is low and clock .phi. is high. Then, in clocked inverter 91, transistors P91, P92 and N92 are on, and transistor N91 is off so that node a is at a high level. In clocked inverter 94 of flip-flop circuit 93, on the other hand, transistors P94 and N94 are off so that the clocked inverter is disabled. Thus, the output level at node a is inverted by inverter 95 so that output node f is at a low level as is the case with input IN.
Suppose, next, that the input signal Vin at input IN remains low, and both clocks .phi. and .phi. go high temporally. Then transistors P91 and N92 turn on, and transistors P92 and N91 turn off in clocked inverter circuit 91, while transistors P93 and N94 turn on, and transistors P94 and N93 turn off in clocked inverter 94. Thus, clocked inverters 91 and 94 are both disabled with the result that output node a is in the high impedance state.
At this time, the potential at node a is initially at a high level as in the previous state. However, since transistors N92, N94 and N95 are on, node a will conduct to nodes c and e, thus dropping the potential at node a. If the voltage drop is large enough to turn transistor P95 and N93 on and turn transistor P93 and N95 off, then the data at node f will be undesirably inverted to the high level.
Next, suppose that a high-level input signal Vin is applied to input IN, clock .phi. is low and clock .phi. is high. In this case transistors P92, N92 and N91 are on, and transistor P91 is off in clocked inverter 91. As a result node a is at the low level. Since transistors P93, P94 and N94 are off, and transistor N93 is off, clocked inverter 94 in flip-flop circuit 93 is disabled. As a result node f goes to the high level, so that the data at input IN is output.
Consider, next, that the input signal Vin remains high, and both clocks .phi. and .phi. go low temporally. Then, transistors P92 and N91 are on, and transistors P91 and N92 are off in clocked inverter 91. In clocked inverter 94 of flip-flop circuit 93, transistors P94 and N93 are on and transistors P93 and N94 are off. Consequently, clocked inverters 91 and 94 are both disabled so that node a is in the high impedance state.
In this case, although the potential at node a is first held at the low level as in the previous state, the potential at node a will be raised if the potential at nodes b and d is at the high level, because transistors P92 and P94 are on. If the increase in potential at node a is large enough to turn transistors P93 and N95 on and turn transistors N93 and P95 off, then data at node f will be inverted.
With the prior art circuit, as described above, the output node of the clocked inverters would be brought to the high-impedance state by a change in the phase angle between opposite polarity clock signals .phi. and .phi.. This may lead to a malfunction. In particular, where high frequency clock signals are needed for high-speed operations, a change in the phases between complementary clock signals is liable to occur. Therefore where such a shift register as described above is provided on the output side of an image memory a problem may arise as to the reliability of operations.